According to study of the present inventors, as for technique of controlling a semiconductor memory device, following technique is considered.
For example, a dynamic random access memory (hereinafter referred to as “DRAM”), which is one of a semiconductor memory device, is mounted in great numbers on various electronic equipments used by us in daily life. And, with needs for lower power consumption and higher performance of equipments in recent years, higher performance such as lower power, higher speed and larger capacity are also strongly demanded for a DRAM mounted.
One of the most effective means for realizing a high performance DRAM is miniaturization of memory cells. By miniaturizing processing dimensions, the memory cells can be smaller. As a result, length of a word line and a bit line connected to the memory cells are reduced. That is, parasitic capacitance of the word lines and the bit lines can be reduced, and therefore, low voltage operation becomes possible and lower power consumption can be realized. Furthermore, since the memory cells become smaller, larger capacity of the memory is obtained and higher performance of the equipment can be realized. Thus, miniaturization of processing dimensions contributes greatly to higher performance of the DRAM.
However, demands for low voltage operation of the DRAM memory cell array is increasing year by year with miniaturization of the processing dimension of semiconductor process to 65 nm and 45 nm nodes and lower power consumption of the DRAM. Accordingly, a voltage applied to the bit line of the DRAM is lowered. In a case where a half pre-charge system is adopted for a sense amplifier of the DRAM, when microscopic data stored in the bit line capacitor is amplified, voltages on a gate of a NMOS transistor and a PMOS transistor of the sense amplifier are also lowered. Therefore, time for amplification of data by the sense amplifier increases and there is a possibility that operation specifications of the DRAM cannot be satisfied. So, unless a voltage applied on each MOS transistor of the sense amplifier is increased or a threshold voltage of the MOS transistor is lowered so as to ensure an execution voltage applied on the gate, bit line capacitance amplified by the sense amplifier must be reduced using a shared MOS (hereinafter referred to as “SHRMOS”) transistor provided between the sense amplifier and the bit line.
As technique of controlling a gate voltage of the SHRMOS transistor as described above, technique disclosed in Japanese Patent Application Laid-Open Publication No. 6-243683 (Patent Document 1) exists. In Patent document 1, technique improving sense speed by controlling the gate voltage of the SHRMOS transistor is disclosed. By controlling the gate voltage of the SHRMOS transistor, the bit line capacitance amplified by the sense amplifier is reduced and the sense speed is improved. And, in re-coupling of the sense amplifier and the memory cell array, lowering of a bit line voltage in a High level side bit at re-coupling can be suppressed by gradually raising the gate voltage of the SHRMOS transistor.